Lattice FPGA provides high-speed glueless interface

Lattice Semiconductor has introduced its LatticeECP2 and LatticeECP2M FPGA interface reference design supporting the Texas Instruments' ADS6000 family of analogue-to-digital converters (ADCs). 

The FPGAs will provide a high-speed glueless interface capable of acquiring 14-bit ADC data at rates up to 120Msample/s from the two to four serial channels found in ADS6000 ADC family devices.

Systems migrating to higher sample rate/ resolution ADCs often require an FPGA with an interface speed of approximately 800Mbit/s to bridge between existing hardware and the newer interface provided by the higher speed ADC.

Typically this can require costly high-end FPGAs, the aim of Lattice is to provide these bridge functions in an optimally sized FPGA at a lower cost.

"Previously, only expensive, high-end FPGAs could interface with ADC bus speeds greater than 600Mbit/s," said Stan Kopec, corporate v-p of marketing. 

"Now our customers can use the LatticeECP2/M FPGA's 840Mbit/s source synchronous interface to design their systems at a significantly lower cost without sacrificing performance or flexibility."

To facilitate design verification, the default configuration of the reference design utilises a new hardware interface card developed by Lattice to work with existing TI and Lattice evaluation boards. 

The LatticeECP2/M family supports logic densities from 6K LUTs up to 95K LUTs, has high performance DSP blocks, supports DDR2 memory interfaces at 533Mbit/s and up to 840Mbit/s generic LVDS performance.