A scalable, efficient multichannel diversity receive

Constructing a communication system with a diversity receiver creates multiple options in device count, power, board space, and signal routing. To reduce the amount of RF components, a direct conversion architecture using a quadrature demodulator can be used.

Constructing the receiver for high performance is difficult due to I/Q mismatch. The architecture requires several components between the RF input and the baseband digital outputs that consume space.

While a super-heterodyne receiver requires only one analog-to-digital converter (ADC), the quadrature demodulator requires a dual ADC to process the real and imaginary analog. This may be acceptable for single carrier systems, but can diversity and a direct conversion receiver be employed efficiently with a multichannel system? Does such a solution scale to more than one or two channels effectively? With new levels of integration in RF and ADC components, a multichannel direct-conversion diversity receiver can be created that is efficient and high performance.

Why diversity?

In communication systems, receiver specifications are set to accommodate a small received input power. Systems such as cellular base transceiver stations (BTS) receive signals from handsets that could be located in environments that greatly attenuate the signal, such as parking garage structures, multifloor buildings or crowded urban areas.

The signal transmitted from the handset will arrive at the BTS many times, having taken many different reflected paths. With only one antenna and receiver, many versions of the same signal will be present at the receive antenna, each with different phase and amplitude.

The signals could add constructively or destructively due to the instantaneous phase relationship. In a mobile phone, for example, the mobile transmitter is not perfectly fixed in space, so the summation at the antenna is continually changing. This is referred to as fast fading and could cause lost reception.

Using diversity antennas increases the chances that a signal with sufficient receive strength will be found, as the antennas are physically separated. While one antenna may be experiencing destructive interference, the other may not. This is diversity.

To demodulate the signal, the communication link is built with a minimum signal-to-noise ratio (SNR) required to demodulate the signal. Diversity allows for a higher probability that a signal will arrive at the BTS above the minimum SNR.

To build a diversity receiver, at least one extra receive path is added for every channel. This may double the cost of the electronics and antenna. However, the cost is justified if it extends the range and quality of the BTS. It can reduce the number of base stations required, reducing the overall network capital cost.

Why ZIF?

A zero intermediate frequency (ZIF) receiver performs a direct conversion from the radio frequency to baseband. There are no intermediate frequencies (IF) that one finds with a superheterodyne receiver.

The advantage here is that RF components are minimized, filtering is made easier and sample rates can be reduced. With diversity, the needed components are now multiplied by two, adding component costs, board space and power. A ZIF receiver saves power and space in the RF section by requiring fewer components.

Why an integrated quadrature receiver?

Constructing a ZIF receiver out of individual components is difficult to do and consumes board space. After the signal is converted to quadrature, there are two baseband analog paths between the mixer outputs and the dual ADC inputs, including separate gain amplifiers and filters.

Mismatches in gain and phase between components along the real and imaginary signal paths create in-band noise as the images normally cancelled in the ideal complex math are now present in the same location as the signal of interest. The in-band, low-level images degrade the in-band SNR and error vector magnitude (EVM), resulting in a high bit error rate (BER)for the communication channel.

However, a highly integrated ZIF receiver can minimize path mismatch issues. The I and Q analog paths are now on the same chip.

The paths will be very well matched as there will be little process, temperature or voltage differences between them. The device includes a complex mixer, a 24-dB programmable gain amplifier (PGA), a programmable eigth order low pass anti-aliasing ADC input filter and a driver amplifier that connects directly to the dual ADC.

It also includes a dc-offset correction block, useful for minimizing the dc offset component of the analog outputs. By integrating all of the necessary functions, the ZIF architecture is made simple for the user, the I and Q paths are matched and good EVM is maintained. By integrating a large portion of the signal chain into a small package, diversity receive paths now can be considered without sacrificing board space or performance.

Fig. 1. For a two-channel ZIF receiver with diversity, eight ADCs are required.

Why an octal ADC?

For a two-channel ZIF receiver with diversity, eight ADCs are required (see Fig. 1). If four 12-bit dual ADCs were used, with parallel data out of each channel, almost 100 data lines would need to be routed and interfaced to the field-programmable gate array (FPGA).

Four clocks would need to be routed for the ADCs. Four 9 x 9mm 12-bit dual ADCs consume over 320 mm2 of board space simply from the packaging. In addition, the routing of nearly 100 data lines easily could double the space needed and require as many data inputs at the FPGA. An octal ADC is an obvious recommendation, but what about power and data lines of eight ADCs in a single package?

Why a serialized octal ADC?

With a new ADC from Texas Instruments, the ADS5282, many of these problems are resolved. At 75 mW per channel and a 9 x 9-mm package, a low power option exists in only 81 mm2, or one-fourth the board space of four duals. Even more importantly, by utilizing a serial LVDS data interface, only one LVDS pair is required per ADC channel. Add an LVDS frame and bit clock, and with 20 physical lines (10 LVDS pairs), the data from eight ADCs can be processed in an FPGA with minimal board space.

Common in ADCs designed for low power in CMOS, 1/f noise is present at baseband. This limits the effective SNR at baseband, which is where a ZIF architecture will use the ADC. The ADC has a selectable mode which suppresses the 1/f noise at baseband (see Fig. 2).

Fig. 2. Notice the 1/f noise (near baseband) is shifted to be at Nyquist once the mode is enabled and the SNR from 0 to 1 MHz is noted in both cases.

The SNR of the ADS5282 at 65MSPS measured to Nyquist (32.5 MHz) is 70.4 dBFS. If the noise floor is assumed flat over Nyquist, then the noise power in the 0 to 1-MHz band would be 85.5 dBFS, due to 15.1 dB of processing gain: 10log10 (32.5 M/1 M).

With an ideal filter that passes the signal and noise up to 1 MHz, 85.5 dBFS would be the expected SNR at the output of the digital filter. However, the measured SNR is 81.9 dBFS in a 1-MHz band, due to the 1/f noise present at baseband. Once the noise suppression mode is enabled, the measured SNR improves to 86.1 dBFS in that band.

The fact that the measured value in the 1-MHz bandwidth (86.1 dBFS) exceeds the expected (70.4 + 15.1 = 85.5 dBFS) is misleading, since it is calculated from a measured Nyquist SNR (70.4 dBFS) that includes high order harmonics (above the ninth) that are counted as noise. This suggests the true Nyquist SNR excluding all harmonics is actually 0.6 dB better, or 71 dBFS.

The ADC also provides decimation by two within each channel to remove the frequency-shifted 1/f noise (still present near Fclk/2), improve the in-band SNR with processing gain and to reduce the high-speed serial LVDS data rate. The included digital filter is kept to a small number of taps to save power, therefore, the processing gain is ~2 dB when the decimation filter is used. Lowering the LVDS rate by using decimation may provide less expensive FPGA options to be considered and provides for an easier timing budget between the ADC and FPGA.

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